STM32L0xx_System_Private_Functions

Functions
void	SystemInit (void)
	Setup the microcontroller system.
void	SystemCoreClockUpdate (void)
	Update SystemCoreClock variable according to Clock Register Values.

Detailed Description

Function Documentation

SystemCoreClockUpdate()

void SystemCoreClockUpdate

(

void

)

Update SystemCoreClock variable according to Clock Register Values.

The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

Note

Each time the core clock (HCLK) changes, this function must be called to update SystemCoreClock variable value. Otherwise, any configuration based on this variable will be incorrect.

- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:

• If SYSCLK source is MSI, SystemCoreClock will contain the MSI value as defined by the MSI range.
• If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
• If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
• If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.

(*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.

(**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

• The result of this function could be not correct when using fractional value for HSE crystal.

SystemInit()

void SystemInit

(

void

)

Setup the microcontroller system.

< Set MSION bit

< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits

< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits

< Reset HSI48ON bit

< Reset HSEBYP bit

< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits